1. Field of the Invention
The invention relates to a method of fabricating a flash memory device and more particularly, to a method of forming a self-aligned floating gate of a flash memory device.
2. Discussion of Related Art
In NAND flash memory devices of 70 nm or less, if a floating gate polysilicon film is deposited after an Isolation Film (ISO) is formed and a floating gate is then formed with an etch process, a short circuit may occur between the ISO and the floating gate due to a short mask overlay margin of the floating gate polysilicon film. Also, a device driving failure may occur because the distance between the ISO and the floating gate is too small.
To avoid this disadvantage, a self-aligned floating gate formation method has been applied in which the floating gate polysilicon film and the ISO can be naturally self-aligned when forming an ISO pattern without using a mask process for the floating gate polysilicon film.
FIGS. 1A and 1B are cross-sectional views of the floating gate of a NAND flash memory device in the related art.
The thickness of a floating gate polysilicon film 16 is necessarily at least 500 Å to form a self-aligned floating gate. To maintain the thickness of the floating gate polysilicon film 16 at a value of at least 500 Å, the thickness of a hard mask nitride film (not shown) must be at least 1000 Å before etching the ISO, to accommodate a subsequent polysilicon Chemical Mechanical Polishing (CMP) process.
Furthermore, upon etching the ISO, an etch profile slope of the hard mask nitride film is not fully 90°. Accordingly, a CMP process is performed after a High Density Plasma (HDP) oxide film 14 is deposited within a trench. Thereafter, when the hard mask nitride film (not shown) is stripped by a wet etch process, the floating gate polysilicon film 16 that is subsequently deposited becomes a negative profile on the tunnel oxide film 12 on the silicon substrate 10, as shown in FIG. 1A, while the hard mask nitride film is stripped by a wet chemical process.
The negative profile of the floating gate polysilicon film 16 becomes exaggerated in the cleaning process and results in a seam or void upon polysilicon deposition. The seam or void is exposed as shown in FIG. 1B during the polysilicon CMP process, and the seam or void portion thus also affects subsequent deposition processes (e.g., the deposition of an oxide-nitride-oxide (ONO) film). Accordingly, a problem arises because materials deposited at the seam or void portion remain as residues when etching the device to form a floating gate module.